Shared system buses or crossbar switches are typically used in a data processing environment to couple two or more master devices to one or more slave devices. A crossbar switch functions as an interconnect via a dedicated, point-to-point interface. The crossbar switch contains one or more arbiters to determine which bus master device is allowed to access any predetermined one of the slave devices when more than one bus master device is attempting to access the same slave device. A shared system bus functions as an interconnect via a shared set of connections. Arbitration circuitry is also used to determine which bus master device is allowed to access any predetermined one of the slave devices when more than one bus master device is attempting to access the bus. Various arbitration protocols exist for determining how and when to award a requested system resource to multiple requesters. Such protocols include, among many, prioritization rankings, round-robin arbitration and forced automatic release at some point after two requesters are acknowledged.
For enhanced efficiency, the communication between a master device and a slave device may be implemented with bursts of information being communicated wherein multiple data access beats are consecutively transferred. Some systems function with a known and defined number of data access beats, such as a cache with a line fill of predetermined length. However, other systems do not always utilize a fixed number of data access beats. In such systems, at least some burst accesses may be variable in length, without utilizing a fixed number of data access beats. Such bursts may be referred to as variable length bursts, unbounded bursts, unlimited bursts, or undefined length burst interchangeably, depending on the terminology in use. In such cases, the master may or may not know the actual or ultimate length (or number of beats) of the burst transfer, and in most cases, the slave device being addressed does not know the ultimate length of the burst, nor does the arbiter(s). The actual length of the burst may be dependent on a number of factors which may cause it to not be possible to predetermine the actual length at the time the burst is initiated, or, it may be predeterminable only by the master, but without a means to indicate the ultimate length of the burst to other components of the system. In such a system, when a particular master device is given control over a slave device to either transmit or receive information therewith using unlimited or variable length burst accesses, a problem results for other master devices seeking to communicate with the same slave device. Known systems have typically handled this operating condition by either forcing the current master device to release control of the slave device or to be permitted to continue use of the slave device until the burst access has completed. For either of these operating extremes, system performance may suffer. When mastership is immediately forced, system performance is degraded from having to perform multiple initiation accesses that have a time overhead penalty. As a result, the advantages of burst operation are reduced if not lost. When mastership is allowed to continue indefinitely, a more urgent or higher priority master device may be forced to wait on the existing undefined length burst access, thereby degrading system performance.
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